The present invention relates to a semiconductor integrated circuit device and, more particularly, to a technology which is effective when applied to a semiconductor integrated circuit device having an SRAM (i.e., Static Random Access Memory).
The SRAM acting as a volatile semiconductor memory device is disclosed in U.S. Pat. No. 4,890,148, for example. The SRAM of this kind is arranged with memory cells at the intersections of complementary data lines and word lines. Each memory cell is composed of a flip-flop circuit and two transfer MISFETs (i.e., Metal insulator Semiconductor Field Effect Transistors). Each transfer MISFET has its one semiconductor region connected with the input/output terminals of the flip-flop circuit and its other semiconductor region connected with the complementary data lines. This transfer MISFET has its gate electrode connected with the word lines, by which its conductivity and inconductivity are controlled. The flip-flop circuit is constructed, as a data storage unit, of two drive MISFETs and two resistor loads. The drive MISFET has its drain region connected with one semiconductor region of one of the transfer MISFETs and its source region connected with a reference voltage line (or source line). The drive MISFET has its gate electrode connected with one semiconductor region of the other transfer MISFET. Each resistor load has its one terminal connected with one semiconductor region of one of the transfer MISFETs and its source region connected with a supply voltage wiring line (or source line). The memory cells of the SRAM of this kind can arrange the resistor loads over the drive MISFETs to reduce the area occupied thereby so that they can highly integrate the SRAM. The memory cells can store data of 1 [bit].